### Journals and Book seriels

### Conferences

__ R. Zhang__, and M. Kaneko, “Robust and Low-Power Digitally-Programmable-Delay-Element Designs Employing Neuron-MOS Mechanism”, ACM Tran. Des. Autom. Electron. Syst. (TODAES), Vol. 20, No. 4, Article 64, (19 pages), September 2015.

__ R. Zhang__, M. Kaneko, and T. Shibata, “An analog VLSI implementation of one-class support vector machine for multiclass classification of highly dimensional vectors,” Jpn. J. Appl. Phys., vol. 53，no. 4. pp. 04EE03. (2014)

__ R. Zhang__ and T. Shibata, “An Analog On-Line-Learning K-means Processor Employing Fully Parallel Self-Converging Circuitry”, J. Analog Integrated Circuits and Signal Processing (Springer)，vol. 75，no. 2，pp. 267-277. (2013)

__ R. Zhang__ and T. Shibata, “Real-Time On-Line-Learning Support Vector Machine Based on A Fully-Parallel Analog VLSI processor,” L. Rutkowski et al. (Eds.): Lecture Notes in Computing Science (LNCS), vol. 7268, Part II, pp. 223-230, Springer, Heidelberg (2012).

P. Zhao, __R. Zhang__ and T. Shibata, “Real-time Visual Tracking Algorithm Employing On-Line Support Vector Machine and Multiple Candidate Regeneration,” L. Rutkowski et al. (Eds.): Lecture Notes in Computing Science (LNCS), vol. 7267, Part I, pp. 617-625, Springer, Heidelberg (2012).

__ R. Zhang__ and T. Shibata, “Fully Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian-Generation Circuits” , Jpn. J. Appl. Phys., vol. 51, no. 4, pp. 04DE10-1 - 04DE10-7. (2012)

Q. Li, Z. Huang, __R. Zhang__ and Y. Inoue , “A low voltage CMOS rectifier for battery-less devices”, IEICE Trans. NOLTA, vol. E93-N, no. 10, Oct. 2010.

__R. Zhang__, T. Nakada and Y. Nakashima, “A Feasibility Study of Programmable Analog Cal-culation Unit for Approximate Computing”, The Fifth International Symposium on Compu-ting and Networking, (CANDAR), Aomori, Japan, Nov. 19-22, 2017 to appear (Outstanding Paper Award).

__R. Zhang__, M. Kaneko, “A Random Access Analog Memory with Master-Slave Structure for Implementing Hexadecimal Logic”, IEEE Int. Conf. System-on-Chip, (SOCC), Munich, Germany, Sept. 5-8, 2017, pp. 7-11.

__R. Zhang__, and M. Kaneko, “A Feasibility Study of Master-Slave Flipflop Design for Hexadecimal Logic”, IEEE Int. Conf. Industrial Electronics and Applications, (IEACon), Nov. 2016.

__R. Zhang__, and M. Kaneko, “A 16-Valued Logic FPGA Architecture Employing Analog Memory Circuit”, IEEE Int. Symp. Circ.s and Syst.s, (ISCAS), Montreal, Canada, May 22-25, 2016, pp. 207-212.

Q. Guo, __R. Zhang__, Q. Li, and Y. Inoue, “An Efficient Cockcroft-Walton Type Charge Pump with Level Shift Control Circuit”, Int. Tech. Conf. Circ.s/Syst.s, Computers and Communications (ITC-CSCC), Seoul, Korea, June 29th- July 2nd, 2015.

__R. Zhang__, and M. Kaneko, “A Feasibility Study of Quaternary FPGA Designs by Implementing Neuron-MOS Mechanism”, IEEE Int. Symp. Circ.s and Syst.s, (ISCAS), Lisbon, Portugal, May 24-27, pp. 942-945. 2015.

__R. Zhang__, and M. Kaneko, “A Quaternary Master-Slave Flip-Flop with Multiple Functions for Multi-Valued Logics”, the 19th Workshop on Synthesis and System Integration of Mixed Information Technologies, Yilan, Taiwan, March 16-17, pp. 193-198. 2015.

__R. Zhang__, and M. Kaneko, “A Temperature and Process Variation Insensitive PDE Circuit Employing Neuron-MOS”, IEEE/ACM Int. Conf. Computer Aided Design, Workshop on VMC, San Jose, USA, Nov. 2014.

__R. Zhang__, and M. Kaneko, “A Feasibility Study on Robust Programmable Delay Element Design based on Neuron-MOS Mechanism”, Great Lake Symposium on VLSI, pp. 21-26, May 2014.

__R. Zhang__, and M. Kaneko, “A Feasibility Study of Robust and Low-Power Programmable Delay Elements Based on Neuron-MOS Mechanism”, IEEJ Technical meeting on Electronic Circuits, ECT-14-015, pp. 75-80 Jan. 2014.

__R. Zhang__, M. Kaneko, and T. Shibata, “A Fully-Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian-Generation Circuits”, Int. Conf. Solid-State Device and Materials, pp. 174-175, Sept. 2013.

__R. Zhang__ and T. Shibata, “A VLSI Hardware Implementation Study of SVDD Algorithm Using Analog Gaussian- Cell Array for On-Chip Learning”, IEEE Int. Workshop on Cellular Nanoscale Networks and their Applications, Turin, Italy, Aug. 29-31, 2012, pp. 74-79.

T. Shibata, __R. Zhang__, Steven P. Levitan, Dmitri Nikonov, and George Bourianoff, “CMOS Supporting Circuitries for Nano-Oscillator-Based Associative Memories”, invited by IEEE Int. Workshop on Cellular Nanoscale Networks and their Applications, Turin, Italy, Aug. 29-31, 2012.

T. Shibata, H. Zhu, R. Bao, P. Zhao and __R. Zhang__, “A VLSI System for Motion Perception and Action Recognition,” in the Proceedings of the 2nd Solid-State Systems Symposium (4S 2012), Ho Chi Minh City, Vietnam, August 22-24, 2012.

__R. Zhang__ and T. Shibata, “An Analog K-means Learning Processor Employing Fully-Parallel Self-Converging Circuitry” , Int. Analog VLSI Workshop, 2011, pp. 91-96.

__ R. Zhang__ and T. Shibata, “A Fully-Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian-Generation Circuits” , Int. Conf. Solid-State Device and Materials, 2011, pp. 174-175.

Q. Li, R.__ Zhang__, Z. Huang and Y. Inoue , “A low voltage CMOS rectifier for wirelessly powered devices”, IEEE ISCAS pp. 873-876, April. 2010.

Q. Li, Z. Huang, M. Jiang, __R. Zhang__ and Y. Inoue ,“A Low Voltage CMOS Rectifier for Low Power Battery-less Devices”, IEICE 23rd Workshop on Circuits and systems , pp. 312-315, April. 2010.

__R. Zhang__, Q. Li, Z. Huang, M. Jiang and Y. Inoue, “An Efficient Charge Pump Based on Cockcroft-Walton Structure”, IEICE 23rd Workshop on Circuits and systems, pp. 316-321, April. 2010.

__ R. Zhang__, Z. Huang, and Y. Inoue, “A Low Breakdown-voltage Charge Pump based on Cockcroft-Walton Structure”, IEEE 8th International Conference on ASIC, pp. 328-331, Oct. 2009.

__R. Zhang__, Y. Inoue, “LSI Circuit Design Education -Differences between China and Japan and the Prospect of their Combination-”, IEEJ Technical meeting on Electronic Circuits, ECT-08-100, Nov. 2008. (Non-referred)