As we know (assume), the road-map of scaling down might reach the end sooner or later. I am trying to explore a different way for computing instead of binary, in order to develope smaller, faster, even smarter VLSI systems. Maybe, the analog-digital-hybrid computing could be one of solutions. Theme
VLSI implementations of multi-valued logic; robust and low power programmable delay elements (PDEs).
Efficient edge-computing systems based on the analog-digital-hybrid VLSI circuits.
School of Electric and Information Engineering (電子情報工学部)
Major： Electric Engineering and its Automatic (電気工学)
Graduate School of Information, Production and System VLSI (情報生産システム研究科)
Dissertation: A charge pump circuit based on Cockcroft-Walton structure preventing device breakdown voltage problems
supervised by Prof. Yasuaki INOUE
Graduate School of Engineering (工学系研究科)
Dissertation: A Fully Parallel Analog VLSI Architecture for Implementing Learning Algorithms
supervised by Prof. Tadashi SHIBATA
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