Renyuan ZHANG (張 任遠)

Assistant Professor (助教)
          Computing Architecture Lab. (コンピューティング・アーキテクチャ研究室)
          情報研究棟B405
          Email:rzhang at is.naist.jp        

As we know (assume), the road-map of scaling down might reach the end sooner or later. I am trying to explore a different way for computing instead of binary, in order to develope smaller, faster, even smarter VLSI systems. Maybe, the analog-digital-hybrid computing could be one of solutions. Theme

Skills and interests

Experience

Education

Publications

Honors & Awards

Lectures

Message sent. Thank you!