研究

研究助成金

著書

  1. Takashi Nakada and Hiroshi Nakamura: "Normally-Off Computing," Springer Japan, 978-4-431-56503-1, (2017)

論文誌

  1. Hoang-Gia VU, Shinya TAKAMAEDA-YAMAZAKI, Takashi NAKADA, and Yasuhiko NAKASHIMA, A Tree-based Checkpointing Architecture for the Dependability of FPGA Computing: IEICE Trans. on Information and Systems, Vol.E101-D, No.2, pp.xx--xx, Feb. (2018) (to appear).
  2. Takashi NAKADA, Tomoki HATANAKA, Hiroshi UEKI, Masanori HAYASHIKOSHI, Toru SHIMIZU, and Hiroshi NAKAMURA, An Energy-Efficient Task Scheduling for Near-realtime Systems with Execution Time Variation: IEICE Trans. on Information and Systems, Vol.E100-D, No.10, pp.2493--2504, Oct. (2017).
  3. Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura: A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip, IEICE Trans. on Information and Systems, Vol.E99-D, No.12, pp.2881--2890, Dec. (2016).
  4. Jun YAO, Yasuhiko NAKASHIMA, Naveen DEVISETTI, Kazuhiro YOSHIMURA, Takashi NAKADA: A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction, IEICE Trans. on Information and Systems, Vol.E97-D,No.12, pp.3092-3100, Dec. (2014)
  5. 有間 英志,薦田 登志矢,中田 尚,三輪 忍,野口 紘希,野村 久美子,安部 恵子,藤田 忍,中村 宏: 低CPU負荷を考慮したSTT-MRAMラスト・レベル・キャッシュの要求性能の解析, 電子情報通信学会論文誌A,Vol.J97-A, No.10, pp.629--647 Oct. (2014)
  6. Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura : Design Aid of Multi-core Embedded Systems with Energy Model, IPSJ Transactions on Advanced Computing Systems, Vol.7, No.3 (ACS46), pp. 37--46, Aug. (2014)
  7. 有間 英志,薦田 登志矢,中田 尚,三輪 忍,中村 宏: キャッシュ電源遮断時の性能ペナルティ削減のための損失データプリフェッチ, 情報処理学会論文誌 コンピューティングシステム, Vol.6, No.3 (ACS43), pp. 118--130, Sep. (2013)
  8. Yukihiro SASAGAWA, Jun YAO, Takashi NAKADA, and Yasuhiko NAKASHIMA: RazorProtector: Maintaining Razor DVS Efficiency in Large IR-drop Zones by an Adaptive Redundant Data-Path, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E95-A No.12 pp.2319-2329 Dec. (2012)
  9. 齊藤光俊, 下岡俊介, D.V.R. Naveen, 大上俊, 吉村和浩, 姚駿, 中田尚, 中島康彦: 線形演算器アレイ型アクセラレータを備えた高電力効率プロセッサの開発, 電子情報通信学会論文誌D, Vol.J95-D, No.9, pp.1729--1737, Sep. (2012)
  10. 岩上拓也,吉村和浩,中田尚,中島康彦: 時分割実行機構による演算器アレイ型アクセラレータの効率化, 情報処理学会論文誌コンピューティングシステム,Vol.5, No.4 (ACS39), pp. 13--23, Aug. (2012)
  11. 吉村和浩, 中田尚, 中島康彦, 北村俊明: 異種命令セットアーキテクチャを持つ高電力効率SMT プロセッサの開発, 電子情報通信学会論文誌D, Vol.J95-D, No.6, pp.1334--1346, Jun. (2012)
  12. 中田尚,吉村和浩,下岡俊介,大上俊,Naveen, D.V.R.,中島康彦:画像処理向け線形アレイアクセラレータの性能評価,情報処理学会論文誌コンピューティングシステム,Vol.5, No.3 (ACS38), pp. 74--85, May (2012)
  13. Kazuhiro Yoshimura, Takuya Iwakami, Takashi Nakada, Jun Yao, Hajime Shimada, Yasuhiko Nakashima: An Instruction Mapping Scheme for FU Array Accelerator, IEICE Transactions on Information and Systems, Vol.E94-D, No.2, pp. 286--297, Feb. (2011)
  14. 柴田章博, 中田尚, 中西正樹, 山下茂, 中島康彦: 量子計算の並列シミュレーションにおける通信量削減手法, 電子情報通信学会論文誌D, Vol.J93-D, No.3, pp.253--264 Mar. (2010)
  15. 中田尚, 片岡晶人, 中島康彦: VLIW型命令キューを持つスーパースカラプロセッサの命令スケジューリング機構, 情報処理学会論文誌コンピューティングシステム, Vol. 2, No. 2(ACS26), pp. 1--15, Jul. (2009)
  16. Hiroshi Nakashima, Masahiro Konishi and Takashi Nakada.: A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions. IPSJ Trans. System LSI Design Methodology, Vol. 1, No. 1, pp. 33--47 (2008).
  17. Masahiro Konishi, Takashi Nakada, Tomoaki Tsumura and Hiroshi Nakashima: An Efficient Analysis of Worst Case Flush Timings for Branch Predictors, IPSJ Transactions on Advanced Computing Systems, Vol. 48, No. SIG8(ACS 18), pp. 127--140 (2007).
  18. 小西昌裕, 中田尚, 津邑公暁, 中島浩: 重複実行省略を用いた割り込みによるマイクロプロセッサの最悪性能予測, 情報処理学会論文誌コンピューティングシステム, Vol. 47, No. SIG12(ACS 15), pp. 159--170 (2006).
  19. 中田尚, 津邑公暁, 中島浩: ワークロード最適化シミュレータの設計と実装, 情報処理学会論文誌コンピューティングシステム, Vol. 46, No. SIG12(ACS 11), pp. 98--109 (2005).
  20. 高崎透, 中田尚, 津邑公暁, 中島浩: 時間軸分割並列化による高速マイクロプロセッサシミュレーション, 情報処理学会論文誌コンピューティングシステム, Vol. 46, No. SIG12(ACS 11), pp. 84--97 (2005).
  21. 中田尚, 中島浩: 高速マイクロプロセッサシミュレータBurstScalar の設計と実装, 情報処理学会論文誌コンピューティングシステム, Vol. 45, No. SIG6(ACS 6), pp. 54--65 (2004).

査読付き国内/国際会議

  1. Takamasa Mitani, Hisakazu Fukuoka, Yuria Hiraga, Takashi Nakada, Yasuhiko Nakashima: "Compression and aggregation for optimizing information transmission in distributed CNN," The Fifth International Symposium on Computing and Networking (CANDAR'17), 7 pages, Nov. (2017)
  2. Renyuan ZHANG, Takashi Nakada, Yasuhiko Nakashima: "A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing," The Fifth International Symposium on Computing and Networking (CANDAR'17), 7 pages, Nov. (2017) Outstanding Paper Award
  3. Takashi Nakada, Hiroyuki Yanagihashi, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura: "Energy-aware Task Scheduling for Near Real-time Periodic Tasks on Heterogeneous Multicore Processors," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 6 pages, Oct. (2017) (Acceptance ratio=29%).
  4. Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima: "CPRring: A Structure-aware Ring-based Checkpointing Architecture for FPGA Computing," The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM2017)(poster), 1 page, Apr. (2017).
  5. Keisuke Fujimoto, Takashi Nakada, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima: "A Multi-Level Power-Capping Mechanism for FPGAs," The 1st. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2017), 7 pages, Apr. (2017). Outstanding M2 Student Award
  6. Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura: "An Adaptive Energy-Efficient Task Scheduling under Execution Time Variation based on Statistical Analysis," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (poster), 7 pages, Sep. (2016).
  7. H. Noguchi, K. Ikegami, S. Takaya, E. Arima, A. Kawasumi, H. Hara, K. Abe, N. Shimomura, J. Ito, S. Fujita, T. Nakada, and H. Nakamura: "4Mb STT-MRAM-based Cache with Memory-Access-aware Power Optimization and Novel Write-Verified-Write / Read-Modified-Write Scheme," 2016 IEEE International Conference of Solid-State Circuits (ISSCC), pp.132--133, Feb. (2016).
  8. Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura: "Energy-Efficient Continuous Task Scheduling for Near Real-time Periodic Tasks," The 8th IEEE International Conference on Internet of Things (iThings), pp.675--681, Dec. (2015)
  9. Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Sususmu Takeda, Shinobu Fujita, Hiroshi Nakamura: "Immediate Sleep: Reducing Energy Impact of Peripheral Circuits in STT-MRAM Caches," The 33rd IEEE International Conference on Computer Design (ICCD'15), pp.157--164, Oct. (2015).
  10. Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura: "Runtime Multi-Optimizations for Energy Efficient On-chip Interconnections," The 33rd IEEE International Conference on Computer Design (ICCD'15) (poster), Oct. (2015).
  11. Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura: "An adaptive energy-efficient task scheduling with energy model," Annual Meeting on Advanced Computing System and Infrastructure (ACSI), Jan. 28 (2015)
  12. Eishi Arima, Shinobu Miwa, Takashi Nakada, Susumu Takeda, Hiroki Noguchi, Shinobu Fujita, Hiroshi Nakamura: "Subarray Level Power-Gating in STT-MRAM Caches to Mitigate Energy Impact of Peripheral Circuits," 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), Work-in-Progress Session (poster), June (2015).
  13. Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura: "Data-aware Power Management for Periodic Real-time Systems with Non-Volatile Memory," 3rd IEEE Nonvolatile Memory Systems and Applications Symposium (NVMSA), 6pages, Aug. (2014)
  14. Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura: "Fine-Grain Power-Gating on STT-MRAM Peripheral Circuits with Locality-aware Access Control," The Memory Forum (in conjunction with the 41st International Symposium on Computer Architecture), June (2014)
  15. Takashi Nakada, Shinobu Miwa, Keisuke Yano, Hiroshi Nakamura, "Performance Modeling for Designing NoC-based Multiprocessors," IEEE International Symposium on Rapid System Prototyping (RSP'13), pp.30--36, Oct. (2013)
  16. Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura, "Power Capping of CPU-GPU Heterogeneous Systems through Coordinating DVFS and Task Mapping," the 31st IEEE International Conference on Computer Design (ICCD'13), pp.349--356, Oct. (2013)
  17. Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura: "D-MRAM cache: Enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory," Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1813--1818, Mar. (2013)
  18. Yukihiro SASAGAWA, Jun YAO, Takashi NAKADA, Yasuhiko NAKASHIMA: "Improving DVS Efficiency by Tolerating IR-drops with an Adaptive Redundant Data-Path," WRA 2011 : 2nd Workshop on Resilient Architectures (in conjuction with MICRO-2011), Dec. (2011)
  19. Jun YAO, Ryoji WATANABE, Kazuhiro YOSHIMURA, Takashi NAKADA, Hajime SHIMADA, Yasuhiko NAKASHIMA: "An Efficient and Reliable 1.5-way Processor by Fusion of Space and Time," Workshop on Dependable and Secure Nanocomputing (WDSN11), pp.69-74, Jun. (2011)
  20. Naveen Devisetti, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Jun Yao, Yasuhiko Nakashima: "LAPP: A Low Power Array Accelerator with Binary Compatibility," Workshop on High-Performance, Power-Aware Computing (HPPAC2011), pp.849--857, May (2011)
  21. 岩上拓矢, 吉村和浩, 中田尚, 中島康彦: "仮想化機構による演算器アレイ型アクセラレータの効率化", 先進的計算基盤システムシンポジウムSACSIS2011論文集, pp.136-143, May. (2011)
  22. 森浩大,大上俊,下岡俊介,吉村和浩,中田尚,中島康彦: "演算器アレイ型アクセラレータのための命令変換手法", 先進的計算基盤システムシンポジウムSACSIS2011論文集(ポスター), pp.207-208, May. (2011)
  23. Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi: "A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors," 16th Pacific Rim International Symposium on Dependable Computing (PRDC'10), pp.237--238, Dec. (2010)
  24. 岩上拓矢, 吉村和浩, 上利宗久, 中田尚, 中島康彦: "プログラマビリティを備える低電力アクセラレータの提案と評価", 先進的計算基盤システムシンポジウムSACSIS2010論文集(poster), May. (2010)
  25. Takuya Iwakami, Munehisa Agari, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima: "Area Optimization of FU Array in Low-Power Accelerators," IEEE Symposium on Low-Power and High-Speed Chips 2010 (poster), Apr. (2010)
  26. Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima, Toshiaki Kitamura: "An Energy Efficient SMT Processor with Heterogeneous Instruction Set Architectures," IASTED Int'l Conf. on Parallel and Distributed Computing and Networks (PDCN2010), pp.201--209, Feb. (2010)
  27. 中田尚, 上利宗久, 中島康彦: 画像処理向け線形アレイVLIWプロセッサ, 先進的計算基盤システムシンポジウムSACSIS2009論文集, pp.293--300, May. (2009)
  28. 吉村和浩, 市来亮人, 中田尚, 中島康彦: 異種命令混在実行プロセッサOROCHIの開発, 電子情報通信学会LSIとシステムのワークショップ2009 (poster), May. (2009) IEEE SSCS Japan Chapter Academic Research Award受賞
  29. Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima: "A Linear Array VLIW Processor for Image Processing," IEEE Symposium on Low-Power and High-Speed Chips 2009 (poster), p. 153, Apr. (2009)
  30. Kazunori Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "A Functional Unit with Small Variety of Highly Reliable Cells," 14th Pacific Rim International Symposium on Dependable Computing (PRDC'08), pp. 353--354, Dec. (2008)
  31. Takashi Nakada, Yasuhiko Nakashima, Hajime Shimada, Kenji Kise, Toshiaki Kitamura: "OROCHI: A Multiple Instruction Set SMT Processor," First International Workshop on New Frontiers in High-performance and Hardware-aware Computing(HipHaC'08), pp. 1--8, Nov. (2008)
  32. Akihito Ichiki, Takashi Nakada and Yasuhiko Nakashima: "A Hybrid Platform for Practical Evaluation of Processors," COOL Chips 2008 (poster), Apr. (2008)
  33. Kazuhiro Yoshimura, Takashi Nakada and Yasuhiko Nakashima: "A QoS Control Method for a Heterogeneous SMT Processor," COOL Chips 2008 (poster), Apr. (2008)
  34. Masahiro Yano, Toru Takasaki, Takashi Nakada and Hiroshi Nakashima: "An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators," 40th Annual Simulation Symposium, pp. 247--255 Mar. (2007).
  35. Hiroshi Nakashima, Masahiro Konishi and Takashi Nakada: "An Accurate and Efficient Simulation-Based Analysis for Worst Case Interruption Delay, Compilers," Compilers, Architecture and Synthesis for Embedded Systems, pp. 2--12 Oct. (2006).
  36. Takashi Nakada, Tomoaki Tsumura and Hiroshi Nakashima: "Design and Implementation of a Workload Specific Simulator," 39th Annual Simulation Symposium, pp. 230--243 Apr. (2006).
  37. 小西昌裕, 中田尚, 津邑公暁, 中島浩: "重複実行省略を用いた割り込みによるマイクロプロセッサの最悪性能予測", 先進的計算基盤システムシンポジウムSACSIS 2006, pp. 143--150 Sep. (2006).
  38. 中田尚, 津邑公暁, 中島浩: "ワークロード最適化シミュレータの設計と実装", 先進的計算基盤システムシンポジウムSACSIS 2005, pp. 329--338 May (2005).
  39. 高崎透, 中田尚, 津邑公暁, 中島浩: "時間軸分割並列化による高速マイクロプロセッサシミュレーション", 先進的計算基盤システムシンポジウムSACSIS 2005, pp. 339--348 May (2005).
  40. Takashi Nakada and Hiroshi Nakashima: "Design and Implementation of a High Speed Microprocessor Simulator BurstScalar," MASCOTS, pp. 364--372 Oct. (2004).
  41. 中田尚, 大野和彦, 中島浩: "高性能マイクロプロセッサの高速シミュレーション", 先進的計算基盤システムシンポジウムSACSIS2003, pp. 89--96 May (2003).
  42. 外崎由里子, 中田尚, 大野和彦, 中島浩: "並列スクリプト言語(Perl)+の実装と設計", 並列処理シンポジウムJSPP2002論文集, pp.241--244 May (2002)

講演等

  1. Takashi Nakada, Toshifumi Nakamoto, Toru Shimizu, Hiroshi Nakamura, "Normally-off Power Management for Sensor Nodes of Global Navigation Satellite System," The 13th International SoC Design Conference, 2 pages, Oct. (2016).
  2. Takashi Nakada, "(Invited paper) Normally-off Computing for Smart Sensor Systems," The 15th International Conference on Computers, Communications and Systems (ICCCS), A3-02, 3 pages, Nov. (2015)
  3. Takashi Nakada, Toru Shimizu, Hiroshi Nakamura, "Normally-off Computing for IoT Systems," The 12th International SoC Design Conference, 2 pages, Nov. (2015).
  4. Susumu Takeda, Hiroki Noguchi, Kumiko Nomura, Shinobu Fujita, Shinobu Miwa, Eishi Arima, Takashi Nakada, Hiroshi Nakamura, "Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors," The 12th International SoC Design Conference, 2 pages (Nov 2015).
  5. 中田尚,"(招待講演)IoTシステムの低電力化をめざすノーマリーオフ・コンピューティング",日本磁気学会第203回研究会, 2015-7-25
  6. Takashi Nakada, Hiroshi Nakamura, "Tutorial-3 Normally-Off Computing: Synergy of New Non-Volatile Memories and Aggressive Power Management", 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Jan. 19 (2015)
  7. Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa, "(Invited Paper) Normally-Off Computing Project : Challenges and Opportunities," The 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Special Session 1S-1, pp.1--5, Jan. (2014)
  8. 中田尚, "組込みシステムのためのノーマリーオフコンピューティング", 電子情報通信学会ソサイエティ大会チュートリアル講演 CT-2-5 Sep. (2013)

解説記事等

  1. 中村宏, 中田尚, 三輪忍: "ノーマリーオフコンピューティング --期待と課題--", 情報処理, Vol. 54, No. 7, pp. 654--660, Jun. (2013)

口頭発表

  1. 柳橋 宏行, 中田 尚, 中村 宏: マルチコア周期実行システムにおける省電力タスクスケジューリングの検討, 情報処理学会研究報告 2014-EMB-35, No. 1, pp.1--7, 2014-11-11. 平成27年度情報処理学会CS領域奨励賞受賞.
  2. 中田尚,田中維人,室啓朗,村上健男,藤崎晋太郎,志村隆則,木下泰三,中村宏: 時空間圧縮と階層化によるセンサネットの省電力化, 信学技報, Vol.114, No.155, CPSY2014-40, pp.179--184, Jul. (2014)
  3. 中田尚,三輪忍,中村宏: NoC型メニーコア設計のための高速キャッシュシミュレーション, 情報処理学会研究報告, Vol.2012-ARC-202, No.15, HOKKE-20, pp.1--6, Dec. (2012)
  4. 渡邊良二, 姚駿, 中田尚, 嶋田創, 中島康彦: サイクルレベルの空間及び時間冗長化技術を融合させた高信頼プロセッサの提案, 平成22年度情報処理学会関西支部大会講演論文集, A-05, Sep. (2010) 情報処理学会関西支部大会学生奨励賞
  5. 大賀健司, 姚駿, 中田尚, 嶋田創, 山下茂, 中島康彦: 少品種高信頼セルを用いた高信頼回路設計手法と信頼性評価手法の提案, 信学技報, Vol.109, No.474, pp.139--146, Mar. (2010) SLDM研究会優秀発表学生賞受賞.
  6. 中田尚, 中島康彦: 線形アレイVLIWプロセッサにおける適応性検討, 情報処理学会研究報告, Vol.2009-ARC-186, No.10, HOKKE-17, pp.1--9, Nov. (2009)
  7. 上利宗久, 中田尚, 中島康彦: 線形アレイ型VLIWプロセッサの面積効率評価, 平成21年度情報処理学会関西支部大会講演論文集, A-03, Sep. (2009)情報処理学会関西支部大会学生奨励賞
  8. 中田尚, 中島康彦: 異種命令混在実行のためのVLIW型命令キューの設計, 情報処理学会研究報告2007-ARC-175, デザインガイア2007, pp.89--94, Nov. (2007)
  9. 中田尚, 高平剛, 津邑公暁, 中島浩: 時分割マイクロプロセッサシミュレーションにおける最適な分割数の調査, 情報処理学会研究報告2005-ARC-167, HOKKE 2006, pp. 199--204 Feb. (2006).
  10. 中田尚, 津邑公暁, 中島浩: ワークロード最適化によるキャッシュシミュレータの高速化, 情報処理学会研究報告2005-ARC-164, SWoPP 2005, pp.97--102 Aug. (2005). 平成18年度情報処理学会CS領域奨励賞受賞.
  11. 高崎透, 中田尚, 中島浩: 高性能マイクロプロセッサシミュレータの時分割並列処理による高速化, 情報処理学会研究報告2005-ARC-161, SHINING 2005, pp. 7--12 Jan. (2005).平成16年度山下記念賞受賞.
  12. 中田尚, 中島浩: 高性能マイクロプロセッサの高速シミュレーションの設計と実装, 情報処理学会研究報告2003-ARC-154, SWoPP 2003, pp. 19--24 Aug. (2003).
  13. 中田尚, 大野和彦, 中島浩: 高性能マイクロプロセッサの高速シミュレーションの構想, 情報処理学会研究報告2002-ARC-149, SWoPP 2002, pp.157--162 Aug. (2002).

特許/出願

  1. 中島康彦, 中田尚: "データ処理装置", PCT/JP2009/005306 (H21.10.13)
  2. 中田尚, 中島康彦: "データ処理装置", 特開2011-008485/特願2009-150788 (H21.6.25)
  3. 中島康彦, 中田尚: "データ処理装置", 特願2008-265312 (H20.10.14)
  4. 中田尚, 中島康彦 ほか: "プロセッサ", 特許第4759026号(H23.6.10)(特開2010-026583/特願2008-183828(H20.7.15))

受賞等

学位論文