Research Activity

(English publications only. Japanese publications are here)

Refereed Journal Articles

  1. Jun YAO, Yasuhiko NAKASHIMA, Naveen DEVISETTI, Kazuhiro YOSHIMURA, Takashi NAKADA: A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction, IEICE Trans., Vol.E97-D,No.12, pp.3092-3100, Dec. (2014)
  2. Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura : Design Aid of Multi-core Embedded Systems with Energy Model, IPSJ Transactions on Advanced Computing Systems, Vol.7, No.3 (ACS46), pp. 37--46, (2014)
  3. Yukihiro SASAGAWA, Jun YAO, Takashi NAKADA, and Yasuhiko NAKASHIMA: RazorProtector: Maintaining Razor DVS Efficiency in Large IR-drop Zones by an Adaptive Redundant Data-Path, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E95-A No.12 pp.2319-2329 Dec. (2012)
  4. Kazuhiro Yoshimura, Takuya Iwakami, Takashi Nakada, Jun Yao, Hajime Shimada, Yasuhiko Nakashima: An Instruction Mapping Scheme for FU Array Accelerator, IEICE Transactions on Information and Systems, Vol.E94-D, No.2, pp. 286--297, Feb. (2011)
  5. Hiroshi Nakashima, Masahiro Konishi and Takashi Nakada.: A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions. IPSJ Trans. System LSI Design Methodology, Vol. 1, No. 1, pp. 33--47 (2008).
  6. Masahiro Konishi, Takashi Nakada, Tomoaki Tsumura and Hiroshi Nakashima: An Efficient Analysis of Worst Case Flush Timings for Branch Predictors, IPSJ Transactions on Advanced Computing Systems, Vol. 48, No. SIG8(ACS 18), pp. 127--140 (2007).

Refereed Conference Papers

  1. Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura: "An adaptive energy-efficient task scheduling with energy model," Annual Meeting on Advanced Computing System and Infrastructure (ACSI), Jan. 28 (2015)
  2. Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura: "Data-aware Power Management for Periodic Real-time Systems with Non-Volatile Memory," 3rd IEEE Nonvolatile Memory Systems and Applications Symposium (NVMSA), 6pages, Aug. (2014)
  3. Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura: "Fine-Grain Power-Gating on STT-MRAM Peripheral Circuits with Locality-aware Access Control," The Memory Forum (in conjunction with the 41st International Symposium on Computer Architecture), June (2014)
  4. Takashi Nakada, Shinobu Miwa, Keisuke Yano, Hiroshi Nakamura, "Performance Modeling for Designing NoC-based Multiprocessors," IEEE International Symposium on Rapid System Prototyping (RSP'13), pp.30--36, Oct. (2013)
  5. Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura, "Power Capping of CPU-GPU Heterogeneous Systems through Coordinating DVFS and Task Mapping," the 31st IEEE International Conference on Computer Design (ICCD'13), Oct. (2013)
  6. Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura: "D-MRAM cache: Enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory," Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1813--1818, Mar. (2013)
  7. Yukihiro SASAGAWA, Jun YAO, Takashi NAKADA, Yasuhiko NAKASHIMA: "Improving DVS Efficiency by Tolerating IR-drops with an Adaptive Redundant Data-Path," WRA 2011 : 2nd Workshop on Resilient Architectures (in conjuction with MICRO-2011), Dec. (2011)
  8. Jun YAO, Ryoji WATANABE, Kazuhiro YOSHIMURA, Takashi NAKADA, Hajime SHIMADA, Yasuhiko NAKASHIMA: "An Efficient and Reliable 1.5-way Processor by Fusion of Space and Time," Workshop on Dependable and Secure Nanocomputing (WDSN11), pp.69-74, Jun. (2011)
  9. Naveen Devisetti, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Jun Yao, Yasuhiko Nakashima: "LAPP: A Low Power Array Accelerator with Binary Compatibility," Workshop on High-Performance, Power-Aware Computing (HPPAC2011), pp.849--857, May (2011)
  10. Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi: "A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors," 16th Pacific Rim International Symposium on Dependable Computing (PRDC'10), pp.237--238, Dec. (2010)
  11. Takuya Iwakami, Munehisa Agari, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima: "Area Optimization of FU Array in Low-Power Accelerators," IEEE Symposium on Low-Power and High-Speed Chips 2010 (poster), Apr. (2010)
  12. Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima, Toshiaki Kitamura: "An Energy Efficient SMT Processor with Heterogeneous Instruction Set Architectures," IASTED Int'l Conf. on Parallel and Distributed Computing and Networks (PDCN2010), pp.201--209, Feb. (2010)
  13. Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima: "A Linear Array VLIW Processor for Image Processing," IEEE Symposium on Low-Power and High-Speed Chips 2009 (poster), p. 153, Apr. (2009)
  14. Kazunori Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "A Functional Unit with Small Variety of Highly Reliable Cells," 14th Pacific Rim International Symposium on Dependable Computing (PRDC'08), pp. 353--354, Dec. (2008)
  15. Takashi Nakada, Yasuhiko Nakashima, Hajime Shimada, Kenji Kise, Toshiaki Kitamura: "OROCHI: A Multiple Instruction Set SMT Processor," First International Workshop on New Frontiers in High-performance and Hardware-aware Computing(HipHaC'08), pp. 1--8, Nov. (2008)
  16. Akihito Ichiki, Takashi Nakada and Yasuhiko Nakashima: "A Hybrid Platform for Practical Evaluation of Processors," COOL Chips 2008 (poster), Apr. (2008)
  17. Kazuhiro Yoshimura, Takashi Nakada and Yasuhiko Nakashima: "A QoS Control Method for a Heterogeneous SMT Processor," COOL Chips 2008 (poster), Apr. (2008)
  18. Masahiro Yano, Toru Takasaki, Takashi Nakada and Hiroshi Nakashima: "An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators," 40th Annual Simulation Symposium, pp. 247--255 Mar. (2007).
  19. Hiroshi Nakashima, Masahiro Konishi and Takashi Nakada: "An Accurate and Efficient Simulation-Based Analysis for Worst Case Interruption Delay, Compilers," Compilers, Architecture and Synthesis for Embedded Systems, pp. 2--12 Oct. (2006).
  20. Takashi Nakada, Tomoaki Tsumura and Hiroshi Nakashima: "Design and Implementation of a Workload Specific Simulator," 39th Annual Simulation Symposium, pp. 230--243 Apr. (2006).
  21. Takashi Nakada and Hiroshi Nakashima: "Design and Implementation of a High Speed Microprocessor Simulator BurstScalar," MASCOTS, pp. 364--372 Oct. (2004).

Invited Talk

  1. Takashi Nakada, Hiroshi Nakamura, "Tutorial-3 Normally-Off Computing: Synergy of New Non-Volatile Memories and Aggressive Power Management", 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Jan. 19 (2015)
  2. Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa, "(Invited Paper) Normally-Off Computing Project : Challenges and Opportunities," The 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Special Session 1S-1, pp.1--5, Jan. (2014)

Award