”­•\˜_•¶ˆê—— 2018”N(2018”N1ŒŽ-2018”N12ŒŽ)

ŸDaiki Yamakawa, Yuki Shibayama, Hiroki Yamane, Yasuhiko Nakashima, and Mutsumi Kimura: "Cellular Neural Network using IGZO Thin Film as Synapses and LSI as Neurons", AM-FPD 2018, Jul, (to be preesnted) (2018)
ŸKeisuke Ikushima, Junpei Shimura, Tokiyoshi Matsuda, Mutsumi Kimura, Hiroki Yamane and Yasuhiko Nakashima: "Research and Development of Ga-Sn-O Thin Films for Application to Neural Networks", AM-FPD 2018, Jul, (to be preesnted) (2018)
ŸRyo Tanaka, Isao Horiuchi, Yukio Mogi, Yasushi Hiroshima, Yasuhiko Nakashima, and Mutsumi Kimura: "Cross-point Device using Ta2O5/Ta Layer for Synapse Element in Neural Network", AM-FPD 2018, Jul, (to be preesnted) (2018) ŸYuki Shibayama, Daiki Yamakawa, Mutsumi Kimura and Yasuhiko Nakashima: "In-Ga-Zn-O Thin Film Synapse in Neural Network Using LSI", IMFEDK 2018, Jun, (to be preesnted) (2018). ŸyxSIG:Outstanding M1 Student Awardz•½‰ê—R—˜ˆŸ, •Ÿ‰ª‹v˜a, ŽO’J„³, ’†“c®, ’†“‡N•F: "‹¤—L CNN ‚ð—p‚¢‚½‚Œø—¦‚È•ªŠ„„˜_ŽÀsƒ‚ƒfƒ‹", xSIG 2018: The 2nd. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, Apr. (2018)
ŸNoriyuki Uetake, Renyuan Zhang, Takashi Nakada, and Yasuhiko Nakashima: "A Programmable Analog Calculation Unit for Vector Computations", IEEE Symposium on Low-Power and High-Speed Chips 2018, Apr. (2018)
ŸTakahiro Ichikura, Ryusuke Yamano, Yuma Kikutani, Renyuan Zhang, and Yasuhiko Nakashima: "EMAXVR: A Programmable Accelerator Employing Near ALU Utilization to DSA", IEEE Symposium on Low-Power and High-Speed Chips 2018, Apr. (2018)
yKeynotezYasuhiko Nakashima: "The End of Normal-computing Era. The Opportunity of Next Computations", International Workshop on Frontiers in Computing Systems and Wireless Communications (FOSCOM 2018), Mar. (2018)
y“dŽqî•ñ’ʐMŠw‰ïŠÖ¼Žx•”Šw¶‰ïŒ¤‹†”­•\u‰‰‰ï§—ãÜz‹e’J—Y^, ŽR–ì—´—C, ˆê‘qFG, ’†“‡N•F: "ƒGƒbƒWƒRƒ“ƒsƒ…[ƒeƒBƒ“ƒOŒü‚¯ƒAƒNƒZƒ‰ƒŒ[ƒ^‚ÌŽÀ‘•‚Æ•]‰¿", “dŽqî•ñ’ʐMŠw‰ïŠÖ¼Žx•”‘æ23‰ñŒ¤‹†”­•\u‰‰‰ï, Mar. (2018)
E‹e’J—Y^, ŽR–ì—´—C, ˆê‘qFG, ’†“‡N•F: "Žž•ªŠ„‘½dŽÀsŒ^ƒVƒXƒgƒŠƒbƒNƒŠƒ“ƒO‚ÌŽÀ‘•‚Æ•]‰¿", MŠw‹Z•ñ, vol.117, no.378, CPSY2017-111, pp.31-36, Jan. (2018)
ŸHoang Gia Vu, Takashi Nakada, and Yasuhiko Nakashima: "Efficient Multitasking on FPGA Using HDL-based Checkpointing", 14th International Symposium on Applied Reconfigurable Computing (ARC2018), pp.1-3, May. (2018)
ŸMutsumi Kimura, Yuki Koga, Hiroki Nakanishi, Tokiyoshi Matsuda, Tomoya Kameda, and Yasuhiko Nakashima: , "In-Ga-Zn-O Thin-Film Devices as Synapse Elements in a Neural Network", IEEE J. Electron Devices Society, pp.100-105, Apr. (2018)
ŸDuc-Phuc NGUYEN, Thi-Hong TRAN, Dinh-Dung LE, Yasuhiko NAKASHIMA: "Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems", International Conference and Exhibition on Visible Light Communications 2018 (ICEVLC2018), Mar. (2018)
ŸHoang-Gia VU, Shinya TAKAMAEDA-YAMAZAKI, Takashi NAKADA, and Yasuhiko NAKASHIMA: "A Tree-based Checkpointing Architecture for the Dependability of FPGA Computing", IEICE Trans., Vol.E101-D, No.2, pp.288-302, Feb. (2018)
ŸD.D. Le, D.P., Nguyen, Thi Hong Tran, Y. Nakashima: "Joint Polar and Run-length Limitted Decoding Scheme for Visible Light Communication Systems", IEICE Communications Express Letter, Vol.7, Issue 1, pp.19-24, Jan. (2018)