発表論文一覧 2017年(2017年1月-2017年12月)

◆Mutsumi Kimura, Yuki Koga, Hiroki Nakanishi, Tokiyoshi Matsuda, Tomoya Kameda, and Yasuhiko Nakashima: , "In-Ga-Zn-O Thin-Film Devices as Synapse Elements in a Neural Network", IEEE J. Electron Devices Society, pp.xxx-xxx, Apr. (2018)
◆Duc-Phuc NGUYEN, Thi-Hong TRAN, Dinh-Dung LE, Yasuhiko NAKASHIMA: "Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems", International Conference and Exhibition on Visible Light Communications 2018 (ICEVLC2018), pp.xxx-xxx, Mar. (2018)
◆Hoang-Gia VU, Shinya TAKAMAEDA-YAMAZAKI, Takashi NAKADA, and Yasuhiko NAKASHIMA: "A Tree-based Checkpointing Architecture for the Dependability of FPGA Computing", IEICE Trans., Vol.E101-D, No.2, pp.xxx-xxx, Feb. (2018)
◆D.D. Le, D.P., Nguyen, Thi Hong Tran, Y. Nakashima: "Joint Polar and Run-length Limitted Decoding Scheme for Visible Light Communication Systems", IEICE Communications Express Letter, (To be published) (2017)
【講】中島康彦: "Approximate Computingとシストリックアレイ", ジスクソフト技術講演会, Dec. (2017)
◆Takamasa Mitani, Hisakazu Fukuoka, Yuria Hiraga, Takashi Nakada and Yasuhiko Nakashima: "Compression and aggregation for optimizing information transmission in distributed CNN", CANDAR'17, REGULAR PAPER, pp.112-118, Nov. (2017)
◆【CANDAR'17 Outstanding Paper Award】Renyuan Zhang, Takashi Nakada and Yasuhiko Nakashima: "A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing", CANDAR'17, REGULAR PAPER, pp.180-186, Nov. (2017)
・Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima: "A Programmable Analog Calculation Unit based on Support Vector Regression", 信学技報, vol.117, no.314, CPSY2017-55, pp.27-32, Nov. (2017)
・福岡久和, 平賀由利亜, 三谷剛正, 中田尚, 中島康彦: "分散CNNにおける圧縮と集約による情報転送の最適化", 信学技報, vol.117, no.314, CPSY2017-59, pp.51-54, Nov. (2017)
・松山且樹, 藤井政圭, 津邑公暁, 中島康彦: "自動メモ化プロセッサにおける復帰アドレス別の再利用率調査とその応用", 情報処理学会研究報告, Vol.2017-ARC-227, No.19, Jul. (2017)
・福岡久和, 三谷剛正, 平賀由利亜, 中田尚, 中島康彦: "動画圧縮技術を利用した分散機械学習における情報伝達効率化", 信学技報, vol.117, no.153, CPSY2017-30, pp.151-155, Jul. (2017)
◆Duc Phuc Nguyen, Dinh Dung Le, Thi Hong Tran, Yasuhiko Nakashima: "NON-RLL DC BALANCE BASED ON NON-SYSTEMATIC POLAR CODE FOR VISIBLE LIGHT COMMUNICATION", Vietnam - Japan Scientific Exchange Meeting 2017 (VJSE2017), Sep. (2017)
【講】中島康彦: "Deep Learningに向けたApproximate Computingとシストリックアレイアーキテクチャ", 革新的コンピューティングの研究開発戦略検討会, JST, Jul. (2017)
【講】中島康彦: "GoogleのTPUにも使われたシストリックアレイアーキテクチャとDeep Learningについて", 富士通研究所技術講演会, Jul. (2017)
・Duc Phuc Nguyen, Dinh Dung Le, Thi Hong Tran, Takashi Nakada, Yasuhiko Nakashima: "A Compact Low-Latency Systematic Successive Cancellation Polar Decoder for Visible Light Communication Systems", 信学技報, vol.117, no.44, CPSY2017-2, pp.3-7, May. (2017)
・Dinh Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima, Son Kiet Nguyen, Huu Thuan Huynh: "A prototype of Dimmable Visible Light Communication System on FPGA", 信学技報, vol.117, no.44, CPSY2017-3, pp.9-13, May. (2017)
・福岡久和, 山野龍佑, 中島康彦: "各種FPGAによる畳み込み演算向けシストリックリングの実装と評価", CPSY研究会, 2017-05-23, May. (2017)
・山野龍佑, 中島康彦: "時分割多重実行によるシストリックリングの面積効率向上手法", 信学技報, vol.117, no.44, CPSY2017-6, pp.27-32, May. (2017)
・平賀由利亜, 三谷剛正, 福岡久和, 中田 尚, 中島康彦: "エッジコンピューティングによる分散ニューラルネットワークの構想", 信学技報, vol.117, no.44, CPSY2017-11, pp.62-67, May. (2017)
◆Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima: "CPRring: A Structure-aware Ring-based Checkpointing Architecture for FPGA Computing", FCCM2017 (poster), May. (2017)
◆【xSIG:Outstanding M2 Student Award】Keisuke Fujimoto, Takashi Nakada, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima: "A Multi-Level Power-Capping Mechanism for FPGAs", xSIG 2017: The 1st. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, Apr. (2017)
◆Mutsumi KIMURA, Hiroki NAKANISHI, Nao NAKAMURA, Tomoharu YOKOYAMA, Tokiyoshi MATSUDA, Tomoya KAMEDA, and Yasuhiko NAKASHIMA: "Simplification of Processing Elements in Cellular Neural Network", SciTechnol-Journal of Electrical Engineering and Electronic Technology, Apr. (2017)
◆【ICFCC Best Oral Presentation Award】Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima: "A Multi-mode Error-Correction Solution based on Split-Concatenation for Wireless Sensor Nodes", The 9th International Conference on Future Computer and Communication(ICFCC 2017), Apr. (2017)
◆Mutsumi Kimura, Ryohei Morita Sumio Sugisaki, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima: "Cellular neural network formed by simplified processing elements composed of thin-film transistors", Elsevier-Journal Neurocomputing 248, pp.112-131, http://dx.doi.org/10.1016/j.neucom.2016.10.085, Mar. (2017)
【講】中島康彦: "99%メモリなアクセラレータIMAX(In Memory Accelerator eXtension)", CAE計算環境研究会@関西シスラボ 第8回シンポジウム, Mar. (2017)
◆Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima: "A Multi-mode Error-Correction Solution based on Split-Concatenation for Wireless Sensor Nodes", Journal of Communications (JCM) Vol.12, No.2, pp.130-136, Doi:10.12720/jcm.12.2.130-136, Feb. (2017)
・一倉孝宏, 山野龍佑, 福岡久和, 中島康彦: "DCNNに最適なCGRAの探索と予備評価", 信学技報, vol.116, no.416, CPSY2016-114, pp.49-54, Jan. (2017)
・Vu Hoang Gia, Takamaeda-Yamazaki Shinya, Nakada Takashi, Nakashima Yasuhiko: "A Framework for Tree-based Checkpointing Architecture for FPGA Computing", IPSJ-SLDM, Jan. (2017)