発表論文一覧 2015年(2015年1月-2015年12月)

【CPSY優秀若手講演賞】亀田友哉, 木村睦, 中島康彦: "セルラニューラルネットワークのシミュレータ開発と評価", 信学技報, vol.115, no.342, CPSY2015-63, pp.13-18, Dec. (2015)
中島康彦: "アルゴリズム記述とCGRA実装を統合するC言語フレームワーク", 信学技報, vol.115, no.342, CPSY2015-65, pp.21-26, Dec. (2015)
・菊谷雄真, Tran Thi Hong, 高前田伸也, 中島康彦: "高位合成ツールVivado HLSとPyCoRAMを用いたFPGAアクセラレータの性能比較", 信学技報, vol.115, no.342, CPSY2015-66, pp.27-32, Dec. (2015)
・三谷剛正, Tran Thi Hong, 高前田伸也, 中島康彦: "HEVCを用いたライトフィールドイメージ圧縮伸張の提案", 信学技報, vol.115, no.342, CPSY2015-67, pp.33-38, Dec. (2015)
・金川宗一郎, NGUYEN Dang Hai, Tran Thi Hong, 高前田伸也, 中島康彦: "EEE802.11ah向け省電力化FFT/IFFT回路に関する研究", 無線通信システム研究会(RCS), Dec. (2015)
・Nguyen Duc Phuc, Tran Thi Hong, Takamaeda Shinya, Yasuhiko Nakashima: "BER/PER Performance of 802.11ah K-best Viterbi Decoder on Fading Channel", 無線通信システム研究会(RCS), Dec. (2015)
・Thi Hong Tran, Dwi Rahma Ariyani, Lina Alfaridah ZH, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima: "Performance Evaluation of K-best Viterbi Decoder for IoT Applications", 信学技報, vol.115, no.342, CPSY2015-70, pp.51-56, Dec. (2015)
【電子情報通信学会コンピュータシステム研究会優秀若手デモ/ポスタ賞】嶋谷知, 加藤大真, 亀田友哉, 藤本啓輔, 竹内昌平, TRAN Thi Hong, 高前田伸也, 中島康彦: "OculusRiftとメニコアシミュレータによる計算ボトルネック可視化システム", 信学技報, vol.115, no.243, CPSY2015-46, pp.5-6, Oct. (2015)
・竹内昌平, TRAN Thi Hong, 高前田伸也, 中島康彦: "低消費電力CGRA EMAXのZynqを用いた実機評価", 信学技報, vol.115, no.243, CPSY2015-51, pp.39-41, Oct. (2015)
◆Tomoya KAMEDA, Mutsumi KIMURA, Yasuhiko NAKASHIMA: "Character Recognition System using Cellular Neural Network suitable for integration on Electronic Displays", Proc. 22nd Int’l Display Workshops(IDW22), Dec. (2015)
◆Shohei Takeuchi, Yuttakon Yuttakonkit, Shinya Takamaeda, Yasuhiko Nakashima: "A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations", Proc. 3rd Int’l Workshop on Computer Systems and Architectures(CSA15), pp.378-384, Dec. (2015)
◆Yuuki Sato, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima: "An Approximate Computing Stack based on Computation Reuse", Proc. 3rd Int’l Workshop on Computer Systems and Architectures(CSA15), pp.385-391, Dec. (2015)
◆Thi Hong Tran, Hiromasa Kato, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima: "Performance Evaluation of 802.11a Viterbi Decoder for IoT Applications", International Conference on Advanced Technologies for Communications 2015 (ATC'15), Ho Chi Minh city, Oct. (2015)
・Yuttakon Yuttakonkit, Tran Thi Hong, 高前田伸也, 中島康彦: "Design Space Exploration of Computational Photography Accelerator", 信学技報CPSY2015-17 SwoPP論文集, pp.7-12, Aug. (2015)
【情報処理学会システム・アーキテクチャ研究会若手奨励賞】枝元正寛, Tran Thi Hong, 高前田伸也, 中島康彦: "ニアメモリ処理アーキテクチャのFPGAへの実装と評価", 信学技報CPSY2015-18 SwoPP論文集, pp.41-46, Aug. (2015)
・竹内昌平, Tran Thi Hong, 高前田伸也, 中島康彦: "Zynqを用いたARM-EMAX密結合アクセラレータの評価", 信学技報CPSY2015-19 SwoPP論文集, pp.47-52, Aug. (2015)
・佐藤裕貴, 津村高範, 津邑公暁, 中島康彦: "自動メモ化プロセッサにおける再利用率向上のための入力値比較手法", 信学技報2015-ARC-216 SwoPP論文集, pp.121-128, Aug. (2015)
◆Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima: "Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators", IEICE Trans., Vol.E98-D, No.12, pp.2141-2149, Dec. (2015)
◆Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima: "A CGRA-based Approach for Accelerating Convolutional Neural Networks", 9th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-15) Turin, Italy, Sep.23-25, (2015)
・Vu Hoang Gia, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima: "A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications", 信学技報, Vol.115, No.109, RECONF2015-15, pp.79-84, Jun. (2015)
・竹内昌平, TRAN Thi Hong, 高前田伸也, 中島康彦: "グラフ処理向けCGRA in Cacheの提案", 信学技報CPSY2015-7, pp.37-41, Apr. (2015)
・金川宗一郎, TRAN Thi Hong, 高前田伸也, 中島康彦: "GPS付なくしもの探知機プロトタイプ開発", 信学技報CPSY2015-15, pp.83-88, Apr. (2015)
・枝元正寛, TRAN Thi Hong, 高前田伸也, 中島康彦: "非定型計算を高速化するニアメモリ処理アーキテクチャ", 信学技報CPSY2015-9, pp.49-52, Apr. (2015)
◆【IEEE Symposium on Low-Power and High-Speed Chips 2015 Featured Poster Award】Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima: "A Parameterized Many Core Simulator for Design Space Exploration", IEEE Symposium on Low-Power and High-Speed Chips 2015 (poster), Apr. (2015)
◆Jun Yao, Yasuhiko Nakashima, Kazutoshi Kobayashi, Makoto Ikeda, Wei Xue, Tomohiro Fujiwara, Ryo Shimizu, Masakazu Tanomoto, Yangtong Xu, Xinliang Wang, Weimin Zheng: "XStenciler: a 7.1GFLOPS/W 16-Core Coprocessor with a Ring Structure for Stencil Applications", IEEE Symposium on Low-Power and High-Speed Chips 2015 (poster), Apr. (2015)
◆Anna Zhang, Jun Yao, Yasuhiko Nakashima: "Lowering the Complexity of k-means Clustering by BFS-dijkstra method for Graph Computing", IEEE Symposium on Low-Power and High-Speed Chips 2015, Apr. (2015)
◆Takumi Tsuzuki, Yuko Hara, Shigeru Yamashita, Yasuhiko Nakashima: "Quantitative Evaluations and Efficient Exploration for Optimal Partially-Programmable Circuits Generation", Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Mar. (2015)