発表論文一覧 2012年(2012年1月-2012年12月)

国際会議
◆Yuko Hara-Azumi, Farshad Firouzi, Saman Kiamehr, and Mehdi Tahoori, "Instruction-Set Extension under Process Variation and Aging Effects," Design, Automation & Test in Europe (DATE), pp. 182-187, Grenoble, France, Mar. 2013.
◆Yuko Hara-Azumi and Hiroyuki Tomiyama, "Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation," International Symposium on Quality Electronic Design (ISQED), pp. 518-523, Santa Clara, CA, USA, Mar. 2013.
◆Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, and Yuko Hara-Azumi, "A Clique-Based Approach to Find Binding and Scheduling Result in Flow-Based Microfluidics Biochips," Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 199-204, Yokohama, Japan, Jan. 2013. (※invited talk)
◆Yuko Hara-Azumi, Takuya Azumi, and Nikil D. Dutt, "VISA Synthesis: Variation-Aware Instruction Set Architecture Synthesis," Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 243-248, Yokohama, Japan, Jan. 2013.
◆Junya Kaida, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Yuko Hara-Azumi, and Koji Inoue, "Task Mapping Techniques for Embedded Many-core SoCs," International SoC Design Conference (ISOCC), pp. 204-207, Jeju, Korea, Nov. 2012.
◆Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis," International Conference on Embedded Software and Systems (ICESS), pp. 1534-1540, Liverpool, UK, Jun. 2012.
国内研究会
・祖父江 亮哉, 原 祐子, 稗田 拓路, 谷口 一徹, 冨山 宏之, "クロック周波数向上のための動作合成におけるコントローラ設計手法," to appear at デザインガイア 2012, 福岡, 2012年11月.
・Yuko Hara-Azumi,Takuya Azumi,Nikil D. Dutt, "Instruction Set Architecture Synthesis Exploiting Process Variation," DAシンポジウム 2012 , 下呂, 2012年8月.
・甲斐田 純也,稗田 拓路,谷口 一徹,冨山 宏之,原 祐子,井上 弘士, "組込みメニーコア向けタスクマッピング手法," DAシンポジウム 2012, 下呂, 2012年8月.
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◆【ICNC'12 Best Paper Award】Kazutaka KAMIMURA, Ryosuke ODA, Tatsuhiro YAMADA, Tomoaki TSUMURA, Hiroshi MATSUO, Yasuhiko NAKASHIMA: "A Speed-Up Technique for an Auto-Memoization Processor by Reusing Partial Results of Instruction Regions", Proc. 3rd Int'l. Conf. on Networking and Computing (ICNC'12), LONG PAPER, Okinawa, Japan, pp.49-57, (Dec. 2012) (doi: 10.1109/ICNC.2012.17) Dec. (2012)
◆Jun YAO, Shogo Okada, Masaki Masuda, Kazutoshi Kobayashi, Yasuhiko Nakashima: "DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and its Case Study of Radiation Stress Test", IEEE Transactions on Nuclear Science, Vol.59, Issue.6, pp.2852-2858, DOI=10.1109/TNS.2012.2223715, Dec. (2012)
中島康彦: "フィルムコンピュータ実現に向けたエミュレータ専用小型CPUの検討", 信学技報CPSY2012-12 SwoPP論文集, pp.19-24, Aug. (2012)
・山中良祐, 姚駿, 中島康彦: "セレクタ部に着目した演算器アレイ型アクセラレータの高信頼化手法", 信学技報CPSY2012-13 SwoPP論文集, pp.25-30, Aug. (2012)
・Tanvir Ahmed, Jun Yao, Yasuhiko Nakashima: "Achieving Near-Optimal Dependability with Minimal Hardware Costs in an FU Array Pro-cessor by Soft Error Rate Monitoring", 研究報告計算機アーキテクチャ(ARC),2012-ARC-201(4),1-6, Aug. (2012)
・神村和敬, 山田龍寛, 小田遼亮, 津邑公暁, 松尾啓志, 中島康彦: "再利用対象区間の細分化による自動メモ化プロセッサの高速化", 研究報告計算機アーキテクチャ(ARC),2012-ARC-201(16),1-8, Aug. (2012)
・大谷友哉, Tanvir Ahmed, 姚駿, 中島康彦: "演算器アレイにおける冗長化オーバヘッドの少ない高信頼化手法の提案", 研究報告計算機アーキテクチャ(ARC),2012-ARC-201(19),1-6, Aug. (2012)
◆Yukihiro SASAGAWA, Jun YAO, Takashi NAKADA, Yasuhiko NAKASHIMA: "RazorProtector: Maintaining Razor DVS Efficiency in Large IR-drop Zones by an Adaptive Redundant Data-Path", IEICE Trans. on VLSI Design and CAD Algorithms, Vol.E95-A, No.12, pp.2319-2329, Dec. (2012)
◆Tanvir Ahmed, Jun Yao, Yasuhiko Nakashima: "Introducing OVP Awareness to Achieve an Efficient Permanent Defect Locating", NANOARCH 2012, pp.43-49, Netherlands, Jul. (2012)
・YAO Jun,NAKASHIMA Yasuhiko: "Deep DVS in FU array by Covering Process Variations with Data-Path Auto-fix", 研究報告計算機アーキテクチャ(ARC), Vol.2012-ARC-200, No.18, pp.1-9, May. (2012)
◆齊藤光俊, 下岡俊介, Devisetti Venkatarama Naveen, 大上俊, 吉村和浩, 姚駿, 中田尚, 中島康彦: "線形演算器アレイ型アクセラレータを備えた高電力効率プロセッサの開発", 電子情報通信学会論文誌D, Vol.J95-D, No.9, pp.1729-1737, Sep. (2012)
◆岩上拓矢, 吉村和浩, 中田尚, 中島康彦: "時分割実行機構による演算器アレイ型アクセラレータの効率化", 情報処理学会論文誌コンピューティングシステム, ACS39, Vol.5, No.4, pp.13-23, Aug. (2012)
◆Jun YAO, Shogo Okada, Hajime Shimada, Kazutoshi Kobayashi and Yasuhiko Nakashima: "DARA: a Low-Cost Reliable Architecture Based on Unhardened Devices and Its Case Study of Radiation Stress Test", 2012 IEEE Nuclear and Space Radiation Effects Conference, Jul. (2012)
◆Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima: "Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication", TAMC2012 (2012)
◆吉村和浩, 中田尚, 中島康彦, 北村俊明: "異種命令セットアーキテクチャを持つ高電力効率SMT プロセッサの開発", 電子情報通信学会論文誌D, Vol.J95-D, No.6, pp.1334-1346, Jun. (2012)
◆中田尚, 吉村和浩, 下岡俊介, 大上俊, Devisetti Venkatarama Naveen, 中島康彦: "画像処理向け線形アレイアクセラレータの性能評価", 情報処理学会論文誌コンピューティングシステム, ACS38, Vol.5, No.3, pp.74-85, May. (2012)
・王昊, 姚駿, 中島康彦: "多様なアクセスパターンに適応するアクセラレータ向けメモリアクセス機構", IPSJ SIG Notes 2012-ARC-199(15), pp.1-4, 2012-03-20, 長崎, Mar. (2012)
・Tanvir Ahmed, Jun Yao and Yasuhiko Nakashima: "Achieving Effective Fault Tolerance in FU array by Adding AVF Awareness", IPSJ SIG Notes 2012-ARC-199(5), pp.1-4, 2012-03-20, 長崎, Mar. (2012)
◆Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "Quantum Walks on the Line with Phase Parameters", IEICE Trans. on Foundations of Computer Science, Vol.E95-D, No.3, pp.722-730, Mar. (2012)